Yannick Bornat - Teaching resources

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====== UART Interface ======

The modules described here make it possible to transfer data from a standard computer to a FPGA board through a UART link. On the computer side, specific software must be used to exchange data, the most convenient is TeraTerm which is already installed on most ENSEIRB-MATMECA computers.

{{ :en202:uart_symbols.png?direct&600 |}}
({{ :en202:uart_symbols.vsd | figure source }})


To send data, it is possible to type ASCii chars on the keyboard, or to select a file containing them. To receive data, it is possible to read ASCii chars in the TeraTerm window, or to store them in a selected file. For more details, go to the [[#TeraTerm configuration]] chapter.

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===== How does UART work =====

In UART mode, data is transmitted on a single signal. Received data arrives through the RX pin, and transmitted data is sent through the TX pin.


===== Receiving Data =====

The module UART_recv analyses data incoming on the RX pin. Once a byte has been received, //dat_en// is set ( ='1' ) during **ONE** clock cycle. Data received is output on //dat// while //dat_en// is set.

the transmission parameters are :
  * 115 200 bps
  * 8 bits / word
  * No parity
  * No flow control
  * 1 stop bit

{{ en202:uart_recv_generic.vhd | VHDL module}}

===== Sending Data =====

The module UART_send builds the waveform to send data on TX. Sending data is only possible when the module is in idle state ( output //busy = '0'// ). To send a byte, assign the 8 bits value to the //dat// input during one clock cycle and assert (set to '1') the //dat_en// input simultaneously.

  * Using the standard //UART_send// module, the //busy// output will be asserted as soon as a byte transfer has started (immediately after //dat_en// is set). The module will become ready as soon as the transfer is empty.
  * Using the //UART_fifo_send// module, a FIFO (First In, First Out) module is implemented before sending data. It is then possible to enqueue several bytes to transmit. The //busy// output is asserted when the internal FIFO is full, and de-asserted as soon as it becomes non-full.


the transmission parameters are :
  * 115 200 bps
  * 8 bits / word
  * No parity
  * No flow control
  * 1 stop bit

  * {{ en202:uart_send_generic.vhd |sending module without FIFO}} 
  * {{ en202:uart_fifo_send.vhd | sending module with embedded FIFO}} (no stable version)

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===== TeraTerm configuration =====

Most FPGA kits have an Embedded USB-connected UART port (often wrongly named //USB to UART converter//). When launching TeraTerm, select the UART COM port. Then go to the //setup// menu nad select //serial port//. It is then possible to set the connection parameters.

Once configured, any char typed is sent to the FPGA board through the UART link  (But is not displayed), and any char sent by the FPGA board is displayed in the terminal window.

==== Sending a file to the Board ====
To send a binary file, use the //file/send file...// window. Then, select the file to send. If sending binary data, check the //binary// box to avoid line feed translations.

==== recording data from the board ====

To record data, select the //file/log...// window. Set the file to record (you may again set the //binary// flag). A new window pops up. Click on //close// to stop recording.