This module provides pseudo-random values. It uses a Linear Feedback Shift Register (LFSR). It is based on the Xilinx application note XAPP052 as reference for LFSR values.

Although generating Random values is possible using the FPGA analog source, this module prefers generating pseudo-random value to improve module portability and give the opportunity to repeat the same computation for debugging.

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Just configure the generic values. The output value rand_val can be used as far as rdy='1'.

If rdy='1', setting update during one clock period will generate the next value in the chain. During the computation, rdy is reset (= '0'), it goes high again as soon as computation is finished and data is available on rand_val.

• SIZE : The size of the LFSR used to generate data.
• OUTPT : Data size of rand_val in bits. This value is refered as n on the symbol schematic. OUTPT must be strictly lower than SIZE.
• CYCLE : The number of LFSR progressions to output a new value (may reduce cycle size if submultiple of (2^size - 1)). Directly affects the number of clock cycles to compute a new value. If this value is below OUTPT a correlation will appear between successive output values.
• SEED : Number of values to drop at the beginning. Used to modify the random sequence if needed.

module file